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april 2010 doc id 8880 rev 4 1/47 1 crx14 iso14443 type-b contactless coupler chip with anti-collision, crc manag ement and anti-clone function features single 5 v 500 mv supply voltage so16n package contactless communication ? iso14443 type-b protocol ? 13.56mhz carrier frequency using an external oscillator ? 106 kbit/s data rate ? 36-byte input/output frame register ? supports frame answer with/without sof/eof ? crc generation and check ? france telecom proprietary anti-clone function ? automated st anti-collision exchange i2c communication ? two-wire i2c serial interface ? supports 400 khz protocol ? 3 chip enable pins ? up to 8 crx14 connected on the same bus 16 1 so16 (mq) 150 mils width www.st.com
contents crx14 2/47 doc id 8880 rev 4 contents 1 summary description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2 signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.1 oscillator (osc1, osc2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.2 antenna output driver (rf out ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.3 antenna input filter (rf in ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.4 transmitter reference voltage (v ref ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.5 serial clock (scl) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.6 serial data (sda) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.7 chip enable (e0, e1, e2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.8 power supply (v cc , gnd, gnd_rf) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3 crx14 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.1 parameter register (00h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.2 input/output frame register (01h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.3 authenticate register (02h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.4 slot marker register (03h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4 crx14 i2c protocol description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4.1 i2c start condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4.2 i2c stop condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4.3 i2c acknowledge bit (ack) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4.4 i2c data input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4.5 i2c memory addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4.6 crx14 i2c write operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.7 crx14 i2c read operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 5 applying the i2c protocol to the crx14 registers . . . . . . . . . . . . . . . . 22 5.1 i2c parameter register protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 5.2 i2c input/output frame register protocol . . . . . . . . . . . . . . . . . . . . . . . . . . 23 5.3 i2c authenticate register protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 5.4 i2c slot marker register protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
crx14 contents doc id 8880 rev 4 3/47 5.5 addresses above location 06h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 6 crx14 iso14443 type- b radio frequency data transfer . . . . . . . . . . . . 26 6.1 output rf data transfer from the crx14 to the picc (request frame) . . 26 6.2 transmission format of request frame characters . . . . . . . . . . . . . . . . . . 26 6.3 request start of frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 6.4 request end of frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 6.5 input rf data transfer from the picc to the crx14 (answer frame) . . . . 28 6.6 transmission format of answer frame characters . . . . . . . . . . . . . . . . . . . 28 6.7 answer start of frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 6.8 answer end of frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 6.9 transmission frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 6.10 crc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 7 tag access using the crx1 4 coupler . . . . . . . . . . . . . . . . . . . . . . . . . . 31 7.1 standard tag command access description . . . . . . . . . . . . . . . . . . . . . . 31 7.2 anti-collision tag sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 8 maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 9 dc and ac parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 10 package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 11 ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 appendix a iso14443 type b c rc calculation . . . . . . . . . . . . . . . . . . . . . . . . . . 44 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
list of tables crx14 4/47 doc id 8880 rev 4 list of tables table 1. signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 table 2. crx14 control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 table 3. parameter register bits description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 table 4. input/output frame register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 table 5. slot marker register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 table 6. device select code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 table 7. crx14 request frame character format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 table 8. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 table 9. i2c ac measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 table 10. i2c input parameters(1,2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 table 11. i2c dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 table 12. i2c ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 table 13. rf out ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 table 14. rf in ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 table 15. so16 narrow - 16 lead plastic small outline, 150 mils body width, package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 table 16. ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 table 17. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
crx14 list of figures doc id 8880 rev 4 5/47 list of figures figure 1. logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 figure 2. logic block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 figure 3. so pin connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 figure 4. crx14 application schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 figure 5. maximum r l value versus bus capacitance (c bus ) for an i 2 c bus . . . . . . . . . . . . . . . . . . 11 figure 6. i2c bus protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 figure 7. crx14 i2c write mode sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 9 figure 8. i2c polling flowchart using ack . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 figure 9. crx14 i2c read modes sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 figure 10. host-to-crx14 transfer: i2c write to parameter register . . . . . . . . . . . . . . . . . . . . . . . . . . 22 figure 11. crx14-to-host transfer: i2c random address read from parameter register . . . . . . . . . . . 22 figure 12. crx14-to-host transfer: i2c current address read from parameter register . . . . . . . . . . . 22 figure 13. host-to-crx14 transfer: i2c write to i/o frame register for iso14443b . . . . . . . . . . . . . . 23 figure 14. crx14-to-host transfer: i2c random address read from i/o frame register for iso14443b 23 figure 15. crx14-to-host transfer: i2c current address read from i/o frame register for iso14443b 24 figure 16. host-to-crx14 transfer: i2c write to slot marker register . . . . . . . . . . . . . . . . . . . . . . . . . 24 figure 17. crx14-to-host transfer: i2c random address read from slot marker register . . . . . . . . . . 25 figure 18. crx14-to-host transfer: i2c current address read from slot marker register . . . . . . . . . . . 25 figure 19. wave transmitted usin g ask modulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 figure 20. crx14 request frame character format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 figure 21. request start of frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 figure 22. request end of frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 figure 23. wave received using bpsk sub- carrier modulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 figure 24. answer start of frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 figure 25. answer end of frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 figure 26. example of a complete transmission frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 figure 27. crc transmission rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 figure 28. standard tag command: request frame transmission. . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 figure 29. standard tag command: answer frame reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 figure 30. standard tag command: complete tag access description. . . . . . . . . . . . . . . . . . . . . . . 32 figure 31. anti-collision st short range me mory sequence (1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 figure 32. anti-collision st short range memory sequence continued . . . . . . . . . . . . . . . . . . . . . . . . 34 figure 33. i2c ac testing i/o waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 figure 34. i2c ac waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 figure 35. crx14 synchronous timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 figure 36. so16 narrow - 16 lead plastic small outline, 150 mils body width, package outline. . . . . . 42
summary description crx14 6/47 doc id 8880 rev 4 1 summary description the crx14 is a contactless coupler that is compliant with the short range iso14443 type-b standard. it is controlled using the two wire i2c bus. the crx14 generates a 13.56 mhz signal on an external antenna. transmitted data are modulated using amplit ude shift keying (ask). received data are demodulated from the picc (proximity integrated coupling card) load variation signal, induced on the antenna, using bit phase shift keying (bpsk) of a 847khz sub-carrier. the transmitted ask wave is 10% modulated. the data transfer rate between the crx14 and the picc is 106 kbit/s in both transmission and reception modes. the crx14 follows the iso14443 type-b recommendation for radio frequency power and signal interface. the crx14 is specifically designed for short range applications that need disposable or secure and reusable, products. the crx14 includes an automated anti-collisio n mechanism that allows it to detect and select any st short range memories that are present at the same time within its range. the anti-collision mechanism is based on the st microelectronics probab ilistic scanning method. the crx14 provides an anti-clone function , from france telecom, which allows the authentication of the st short range memories. using the crx14 single chip coupler, therefore, it is easy to design a reader, with authentication capability and to build an end application with a high level of security at low cost. the crx14 provides a complete analog interface, compliant with the iso14443 type-b recommendations for radio-frequency power and signal interfacing. with it, any iso14443 type-b picc products can be powered and have their data transmission controlled via a simple antenna. the crx14 is fabricated in stmicroelectroni cs high endurance single poly-silicon cmos technology. the crx14 is organized as 4 different blocks (see figure 2 ): the i2c bus controller. it handles the serial connection with the application host. it is compliant with the 400khz i2c bus specification, and controls the read/write access to all the crx14 registers. the ram buffer. it is bi-directional. . it st ores all the request frame bytes to be transmitted to the picc, and all the received bytes sent by the picc on the answer frame. the transmitter. it powers the piccs by generating a 13.56mhz signal on an external antenna. the resulting field is 10% modulated using ask (amplitude shift keying) for outgoing data. the receiver. it demodulates the signal generated on the antenna by the load variation of the picc. the resu lting signal is decoded by a 847khz bpsk (binary phase shift keying) sub-carrier decoder. the crx14 is designed to be connected to a digital host (microcontroller or asic). this host has to manage the entire communication protocol in both transmit and receive modes, through the i2c serial bus.
crx14 summary description doc id 8880 rev 4 7/47 figure 1. logic diagram table 1. signal names signal description rf out antenna output driver rf in antenna input filter osc1 oscillator input osc2 oscillator output e0, e1, e2 chip enable inputs sda i2c bi-directional data scl i2c clock v cc power supply gnd ground v ref transmitter reference voltage gnd_rf ground for rf circuitry ai06828b rf out crx14 rf in osc1 scl sda e0 e1 e2 gnd gnd_rf v cc v ref antenna osc2
summary description crx14 8/47 doc id 8880 rev 4 figure 2. logic block diagram figure 3. so pin connections ai10910 rf out crx14 rf in osc1 scl sda e0 e1 e2 gnd gnd_rf v cc v ref antenna transmitter receiver i2c bus controller ram buffer osc2 1 ai10911 2 3 4 16 15 14 13 gnd e1 osc2 osc1 rf in v ref gnd_rf e0 so16 5 6 7 8 12 11 10 9 sda gnd scl gnd_rf e2 gnd rf out v cc
crx14 signal description doc id 8880 rev 4 9/47 2 signal description see figure 1: logic diagram , and table 1: signal names , for an overview of the signals connected to this device. 2.1 oscillator (osc1, osc2) the osc1 and osc2 pins are internally con nected to the on-chip oscillator circuit. the osc1 pin is the input pin, the osc2 is the output pin. for correct operation of the crx14, it is required to connect a 13.56mhz quartz crystal across osc1 and osc2. if an external clock is used, it must be connected to osc1 and osc2 must be left open. 2.2 antenna output driver (rf out ) the antenna output driver pin, rf out , generates the modulated 13.56mhz signal on the antenna. care must be taken as it will not withstand a short-circuit. rf out has to be connected to the antenna circuitry as shown in figure 4: crx14 application schematic the lrc antenna circuitry must be connected across the rf out pin and gnd. 2.3 antenna input filter (rf in ) the antenna input filter of the crx14, rf in , has to be connected to the external antenna through an adapter circuit, as shown in figure 4 . the input filter demodulates the signal generated on the antenna by the load variation of the picc. the resulting signal is then decoded by the 84 7khz bpsk decoder. 2.4 transmitter reference voltage (v ref ) the transmitter reference voltage input, v ref , provides a reference voltage used by the output driver for ask modulation. the transmitter reference voltage input should be connected to an external capacitor, as shown in figure 4 . 2.5 serial clock (scl) the scl input pin is used to strobe all i2c data in and out of the crx14. in applications where this line is used by slave devices to synch ronize the bus to a slower clock, the master must have an open drain output, and a pull-up resistor must be connected from the serial clock (scl) to v cc . ( figure 5 indicates how the value of the pull-up resistor can be calculated). in most applications, though, this method of synchronization is not employed, and so the pull-up resistor is not necessary, provided that the master has a push-pull (rather than open drain) output.
signal description crx14 10/47 doc id 8880 rev 4 2.6 serial data (sda) the sda signal is bi-directional. it is used to tr ansfer i2c data in and out of the crx14. it is an open drain output that may be wire-or?ed with other open drain or open collector signals on the bus. a pull-up resistor must be connected from serial data (sda) to v cc . ( figure 5 indicates how the value of the pull-up resistor can be calculated). 2.7 chip enable (e0, e1, e2) the chip enable inputs e0, e1, e2 are used to set and reset the value on the three least significant bits (b3, b2, b1) of the 7-bit i2c device select code. they are used for hardwired addressing, allowing up to eight crx14 devices to be addressed on the same i2c bus. these inputs may be driven dynamically or tied to v cc or gnd to establish the device select code (note that the v il and v ih levels for the inputs are cmos compatible, not ttl compatible). when left open, e0, e1 and e2 are internally read at the logic level 0 due to the internal pull- down resistors connect ed to each inputs. 2.8 power supply (v cc , gnd, gnd_rf) power is supplied to the crx14 using the v cc , gnd and gnd_rf pins. v cc is the power supply pin that supplies the power (+5v) for all crx14 operations. the gnd and gnd_rf pins are ground connections. they must be connected together. decoupling capacitors should be connected between the v cc supply voltage pin, the gnd ground pin and the gnd_ref ground pin to filter the power line, as shown in figure 4 . figure 4. crx14 application schematic v ref 1 rf in 2 e0 3 e1 4 e2 5 gnd_rf 6 gnd 7 gnd 8 sda 9 scl 10 gnd 11 osc2 12 osc1 13 gnd_rf 14 rf out 15 v cc 16 u1 crx14 x1 13.56mhz c1 7pf50v c2 7pf50v c3 22nf50v c8 100pf50v c8' 8pf50v c7 120pf50v c7' 33pf50v v cc v cc c6 100nf50v + c4 22uf 10v fl4 0r fl5 0r fl6 0r fl7 wurth 742-792-042 r7 0r r8 0r r1 opt ant1 ant2 e0 e1 e2 scl sda 1 2 3 4 j1 r2 0r r3 opt r4 0r r5 opt r6 0r v cc d1 1n4148 (optional) c5 10pf50v ai10952
crx14 signal description doc id 8880 rev 4 11/47 figure 5. maximum r l value versus bus capacitance (c bus ) for an i 2 c bus ai01665 v cc c bus sda r l master r l scl c bus 100 0 4 8 12 16 20 c bus (pf) maximum rp value (k ) 10 1000 fc = 400khz fc = 100khz
crx14 registers crx14 12/47 doc id 8880 rev 4 3 crx14 registers the crx14 chip coupler contains six volatile regi sters. it is entirely controlled, at both digital and analog level, using the four registers listed below and shown in ta bl e 2 : parameter register input/output frame register authentication register slot marker register the other 3 registers are located at addresses 02h, 04h and 05h. they are ?st reserved?, and must not be used in end-user applications. in the i2c protocol, all data bytes are transmitted most significant byte first, with each byte transmitted most significant bit first. 3.1 parameter register (00h) the parameter register is an 8-bit volatile register used to configure the crx14, and thus, to customize the circuit behavior. the parameter register is located at the i2c address 00h and it is accessible in i2c read and write modes. its default value, 00h, puts the crx14 in standard iso14443 type-b configuration. table 2. crx14 control registers address length access purpose 00h parameter register 1 byte w set parameter register r read parameter register 01h input/output frame register 36 bytes w store and send request frame to the picc. wait for picc answer frame r transfer picc answered frame data to host 02h authenticate register na w start the authentication process r get the authentication status 03h slot marker register 1 byte w launch the automated anti-collision process from slot_0 to slot_15 r return data ffh 04h st reserved na r and w st reserved. must not be used 05h st reserved na r and w st reserved. must not be used table 3. parameter register bits description bit control value description b 0 frame standard 0 iso14443 type-b frame management 1 rfu (1) b 1 rfu 0 not used
crx14 crx14 registers doc id 8880 rev 4 13/47 3.2 input/output frame register (01h) the input/output frame register is a 36-byte buffer that is accessed serially from byte 0 through to byte 35 (see ta b l e 4 ). it is located at the i2c address 01h. the input/output frame register is the buffer in which the crx14 stores the data bytes of the request frame to be sent to the picc. it automatically stores the data bytes of the answer frame received from the picc. the first byte (byte 0) of the input/output frame register is used to store the frame length for both transmission and reception. when accessed in i2c write mode , the register stores the request frame bytes that are to be transmitted to the picc. byte 0 must be set with the request frame length (in bytes) and the frame is stored from byte 1 onwards. at the end of the transmis sion, the 16-bit crc is automatically added. after the transmission, the crx14 wait for the picc to send back an answer frame. when correctly decoded, the picc answer frame bytes are stored in the input/output frame register from byte 1 onwards. byte 0 stores the number of bytes received from the picc. when accessed in i2c read mode, the input/output register sends back the last picc answer frame bytes, if any, with byte 0 transmitted first. the 16-bit crc is not stored, and it is not sent back on the i2c bus. the input/output frame register is set to all 00h between transmission and reception. if there is no answer from the picc, byte 0 is set to 00h. in the case of a crc error, byte 0 is set to ffh, and the data bytes are discarded and not appended in the register. the crx14 input/output frame register is so designed as to generate all the st short range memory command frames. it can also generate all standardized iso14443 type-b command frames like reqb, slot-marker, attrib, halt, and get all the answers like atqb, or answer to attrib. all iso14443 type-b compliant piccs can be accessed by the crx14 provided that their data frame exchange is not longer than 35 bytes in both request and answer. b 2 answer frame format 0 answer picc frames are delimited by sof and eof 1 answer picc frames do not provide sof and eof delimiters b 3 ask modulation depth 0 10% ask modulation depth mode 1rfu b 4 carrier frequency 0 13.56mhz carrier on rf out is off 1 13.56mhz carrier on rf out is on b 5 t wdg answer delay watchdog b5=0, b6=0: watchdog time-out = 500s to be used for read b5=0, b6=1: watchdog time-out = 5m s to be used for authentication b5=1, b6=0: watchdog time-out = 10ms to be used for write b5=1, b6=1: watchdog time-out = 309ms to be used for mcu timings b 6 b 7 rfu 0 not used 1. rfu = reserved for future use. table 3. parameter register bits description (continued) bit control value description
crx14 registers crx14 14/47 doc id 8880 rev 4 3.3 authenticate register (02h) the authenticate register is used to trigger the complete authentication exchange between the crx14 and the secured st short range memory. it is located at the i2c address 02h. the authentication system is based on a proprietary challenge/response mechanism that allows the application software to authenticate a secured st short range memory of the srxxxx family. a reader designed with the crx14 can check the authenticity of a memory device and protect the application syste m against silicon copies or emulators. a complete description of the authenticatio n system is available under non disclosure agreement (nda) with stmicroelectronics. for more details about this crx14 function, please contact the nearest stmicroelectronics sales office. 3.4 slot marker register (03h) the slot marker register is located at the i2c address 03h. it is used to trigger an automated anti-collision sequence between the crx14 and any st short range memory present in the electromagnetic field. with one i2c access, the crx14 launches a complete stream of commands starting from pcall16(), slot_marker(1), slot_marker(2) up to slot_marker(15), and stores all the identified chip_ids into the input/output frame register (i2c address 01h). this automated anti-collisi on sequence simplifies the hos t software development and reduces the time needed to inte rrogate the 16 slots of the stmicroelectronics anti-collision mechanism. when accessed in i2c write mode, the slot marker register starts generating the sequence of anti-collision commands. af ter each command, the crx14 wa it for the st short range memory answer frame which contains the chip_id. the validity of the answer is checked and stored into the corresponding status slot bit (byte 1 and byte 2 as described in ta bl e 5 ). if the answer is correct, the status slot bit is set to ?1? and the chip_id is stored into the corresponding slot_register. if no answer is detected, the status slot bit is set to ?0?, and the corresponding slot_register is set to 00h. if a crc error is detected, the status slot bit is set to ?0?, and the corresponding slot_register is set to ffh. each time the slot marker register is accessed in i2c write mode, byte 0 of the input/output frame register is set to 18, bytes 1 and 2 provide status bits slot information, and bytes 3 to 18 store the corresponding chip_id or error code. the slot marker register cannot be accessed in i2c read mo de. all the anti-collision data can be accessed by reading the input/output frame register at the i2c address 01h. table 4. input/output frame register description byte 0 byte 1 byte 2 byte 3 ... byte 34 byte 35 frame length first data byte sec ond data byte last data byte <------------- request and answer frame bytes exchanged on the rf -------------> 00h no byte transmitted ffh crc error xxh number of transmitted bytes
crx14 crx14 registers doc id 8880 rev 4 15/47 table 5. slot marker register description b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 byte 0 number of stored bytes: fixed to 18 byte 1 status slot bit 7 status slot bit 6 status slot bit 5 status slot bit 4 status slot bit 3 status slot bit 2 status slot bit 1 status slot bit 0 byte 2 status slot bit 15 status slot bit 14 status slot bit 13 status slot bit 12 status slot bit 11 status slot bit 10 status slot bit 9 status slot bit 8 byte 3 slot_register 0 = chip_id value detected in slot 0 byte 4 slot_register 1 = chip_id value detected in slot 1 byte 5 slot_register 2 = chip_id value detected in slot 2 byte 6 slot_register 3 = chip_id value detected in slot 3 byte n ..... byte 17 slot_register 14 = chip_id value detected in slot 14 byte 18 slot_register 15 = chip_id value detected in slot 15 status bit value description: 1: no error detected. the chip_id stored in the slot register is valid. 0: error detected ? slot register = 00h: no answer frame detected from st short range memory ? slot register = ffh: answer frame detected with crc error. collision may have occurred
crx14 i2c protocol description crx14 16/47 doc id 8880 rev 4 4 crx14 i2c protocol description the crx14 is compatible with the i2c serial bus memory standard, which is a two-wire serial interface that uses a bi-directional data bus and serial clock. the crx14 has a pre-programmed, 4-bit identification code, ?1010? (as shown in ta b l e 6 ), that corresponds to the i2c bus definition. with this code and the three chip enable inputs (e2, e1, e0) up to eight crx14 devices can be connected to the i2c bus, and selected individually. the crx14 behaves as a slave device in the i2c protocol, with all crx14 operations synchronized to the serial clock. i2c read and write operations are initiated by a start condition, generated by the bus master. the start condition is followed by the device select code and by a read/write bit (r/w ). it is terminated by an acknowledge bit. the device select code consists of seven bits (as shown in ta b l e 6 ): the device code (first four bits) plus three bits corresponding to the states of the three chip enable inputs, e2, e1 and e0, respectively when data is written to the crx14, the device inserts an acknowledge bit (9th bit) after the bus master?s 8-bit transmission. when the bus master reads data, it also acknowledges the receipt of the data byte by inserting an acknowledge bit (9th bit). data transfers are terminated by a stop condition after an ack for write, or after a noack for read. the crx14 supports the i2c protocol, as summarized in figure 6 . any device that sends data on to the bus, is defined as a transmitter, and any device that reads the data, as a receiver. the device that controls the data transfer is known as the master, and the other, as the slave. a data transfer can only be initiated by the master, which also provides the serial clock for synchronization. the crx14 is always a slave device in all i2c communications. all data are transmitted most significant bit (msb) first. 4.1 i2c start condition start is identified by a high-to-low transition of the serial data line, sda, while the serial clock, scl, is stable in the high state. a start condition must precede any data transfer command. table 6. device select code device code chip enable rw b7 b6 b5 b4 b3 b2 b1 b0 crx14 select 1 0 1 0 e2 e1 e0 rw
crx14 crx14 i2c protocol description doc id 8880 rev 4 17/47 the crx14 continuously monitors the sda and scl lines for a start condition (except during radio frequency data exchanges), and will not resp ond unless one is sent. 4.2 i2c stop condition stop is identified by a low-to-high transition of the serial data line, sda, while the serial clock, scl, is stable in the high state. a stop condition terminates communications between the crx14 and the bus master. a stop condition at the end of an i2c read command, after (and only after) a noack, forces the crx14 into its stand-by state. a stop condition at the end of an i2c write command triggers the radio frequency data exchange between the crx14 and the picc. 4.3 i2c acknowledge bit (ack) an acknowledge bit is used to indicate a successful data transfer on the i2c bus. the bus transmitter, either master or slave, releases the serial data line, sda, after sending 8 bits of data. during the 9th clock pulse the receiver pulls the sda line low to acknowledge the receipt of the 8 data bits. 4.4 i2c data input during data input, the crx14 samples the sda bus signal on the rising edge of the serial clock, scl. for correct device operation, the sda signal must be stable during the low-to- high serial clock transition, and the data must change only when the scl line is low.
crx14 i2c protocol description crx14 18/47 doc id 8880 rev 4 figure 6. i2c bus protocol 4.5 i2c memory addressing to start up communication with the crx14, the bus master must initiate a start condition. then, the bus master sends 8 bits (with the most significant bit first) on the serial data line, sda. these bits consist of the device select code (7 bits) plus a rw bit. according to the i2c bus definition, the seven most significant bits of the device select code are the device type identifier. for the crx14, these bits are defined as shown in ta bl e 6 . the 8th bit is the read/write bit (rw ). it is set to ?1? for i2c read, and to ?0? for i2c write operations. if the data sent by the bus master matches the device select code of a crx14 device, the corresponding device returns an acknowledgment on the sda bus during the 9 th bit time. the crx14 devices whose device select codes do not correspond to the data sent, generate a no-ack. they deselect themselves from the bus and go into stand-by mode. scl sda scl sda sda start condition sda input sda change ai00792 stop condition 1 23 7 89 msb ack start condition scl 1 23 7 89 msb ack stop condition
crx14 crx14 i2c protocol description doc id 8880 rev 4 19/47 4.6 crx14 i2c write operations the bus master sends a start condition, followed by a device select code and the r/w bit set to ?0?. the crx14 that corresponds to the device select code, acknowledges and waits for the bus master to send the byte address of the register that is to be written to. after receipt of the address, the crx14 returns another ack, and waits for the bus master to send the data bytes that are to be written. in the crx14 i2c write mode, the bus master may sends one or more data bytes depending on the selected register. the crx14 replies with an ack after each data byte received. the bus master terminates the transfer by generating a stop condition. the stop condition at the end of a write access to the input/output frame, authenticate or anti-collision register causes the radi o frequency data exchange between the crx14 and the picc to be started. during the radio frequency data exchange, the crx14 disconnects itself from the i2c bus. the time (t rfex ) needed to complete the exchange is not fixed as it depends on the picc command format. to know when the exchange is complete, the bus master uses an ack polling sequence as shown in figure 8 . it consists of the following: initial condition: a radio frequency data exchange is in progress. step 1: the master issues a start condition followed by the first byte of the new instruction (device select code plus r/w bit). step 2: if the crx14 is busy, no ack is returned and the master goes back to step 1. if the crx14 has completed the radio frequency data exchange, it responds with an ack, indicating that it is ready to receive the second part of the next instruction (the first byte of this instruction being sent during step 1). figure 7. crx14 i2c write mode sequence ai09265 stop data n ack ack start crx14 write dev sel byte addr data 1 data 2 data 3 ack ack ack ack r/w bus master bus slave
crx14 i2c protocol description crx14 20/47 doc id 8880 rev 4 figure 8. i2c polling flowchart using ack 4.7 crx14 i2c read operations to send a read command, the bus master sends a start condition, followed by a device select code and the r/w bit set to ?1?. the crx14 that corresponds to the device sele ct code acknowledges and outputs the first data byte of the addressed register. to select a specific register, a dummy write command must first be issued, giving an address byte but no data bytes, as shown in the bottom half of figure 9 . this causes the new address to be stored in the internal address pointer, for use by the read command that immediately follows the dummy write command. in the i2c read mode, the crx14 may read one or more data bytes depending on the selected register. the bus master has to generate an ack after each data byte to read all the register data in a continuous stream. only the last data byte should not be followed by an ack. the master then terminates the transfer with a stop condition, as shown in figure 9 . radio frequency data exchange in progress start condition device select code with r/w=1 ack returned next operation is addressing the crx14 restart stop stop proceed to read operation yes no first byte of instruction with r/w = 1 already decoded by the crx14 no yes ai09234
crx14 crx14 i2c protocol description doc id 8880 rev 4 21/47 after reading each byte, the crx14 waits for the master to send an ack during the 9 th bit time. if the master does not return an ack within this time, the crx14 terminates the data transfer and switches to stand-by mode. figure 9. crx14 i2c read modes sequences start crx14 read dev sel data 1 data 2 data 3 ai09266 stop data n ack ack ack r/w ack noack bus master bus slave ack data 4 start crx14 read dev sel address ack bus master bus slave r/w ack dev sel data 1 stop data n ack ack r/w ack noack data 2 re-start i2c current address read i2c random address read
applying the i2c protocol to the crx14 registers crx14 22/47 doc id 8880 rev 4 5 applying the i2c protocol to the crx14 registers 5.1 i2c parameter register protocol figure 10 shows how new data is written to the parameter register. the new value becomes active after the i2c stop condition. figure 11 shows how to read the parameter register contents. the crx14 sends and re- sends the parameter register contents until it receives a noack from the i2c host. the crx14 supports the i2c current address and random address read modes. the current address read mode can be used if the previous command was issued to the register where the read is to take place. figure 10. host-to-crx14 transfer: i2c write to parameter register figure 11. crx14-to-host transfer: i2c random address read from parameter register figure 12. crx14-to-host transfer: i2c current address read from parameter register s t a r t 1010xxx 00h data s t o p ack ack ack register byte value parameter register address device select code bus master crx14 write bus slave ai09240 r/w s t a r t 1010xxx 00h data s t o p ack ack ack register byte value parameter register address device select code bus master crx14 read bus slave ai09241 r e s t a r t 1010xxx r/w device select code r/w noack data s t o p ack register byte value bus master crx14 read bus slave ai09242 s t a r t 1010xxx device select code r/w noack
crx14 applying the i2c protocol to the crx14 registers doc id 8880 rev 4 23/47 5.2 i2c input/output frame register protocol figure 13 shows how to store a picc request frame command of n bytes into the input/output frame register. after the i2c stop condition, the request frame is rf transmitted in the iso14443 type-b format. the crx14 then waits for the picc an swer frame which will also be stored in the input/output frame register. the request frame is over-written by the answer frame. figure 14 shows how to read an n -byte picc answer frame. the two crc bytes generated by the picc are not stored. the crx14 continues to output data bytes until a noack has been generated by the i2c host, and received by the crx14. after all 36 bytes have been output, the crx14 ?rolls over?, and starts outputting from the start of the input/output frame register again. the crx14 supports the i2c current address and random address read modes. the current address read mode can be used if the previous command was issued to the register where the read is to take place. figure 13. host-to-crx14 transfer: i2c write to i/o frame register for iso14443b figure 14. crx14-to-host transfer: i2c random address read from i/o frame register for iso14443b s t a r t 1 0 1 0 xx x 01h n s t o p ack ack ack request frame length n input/output register address device select code bus master crx14 write bus slave ai09243 r/w data 1 data 2 picc command parameter picc command code data n picc command parameter picc command parameter ack ack ack ack s t a r t 1010xxx 01h n s t o p ack ack ack received frame length input/output register address device select code bus master crx14 read bus slave ai09243 r/w data1 data 2 answer frame data answer frame data data n answer frame data answer frame data noack ack ack ack r e s t a r t 10 1 0xxx device select code r/w ack
applying the i2c protocol to the crx14 registers crx14 24/47 doc id 8880 rev 4 figure 15. crx14-to-host transfer: i2c current address read from i/o frame register for iso14443b 5.3 i2c authenticate register protocol for information please contact your nearest stmicroelectronics sales office. 5.4 i2c slot marker register protocol an i2c write command to the slot marker register generates an automated sixteen- command loop (see figure 16 for a description of the command). all the answers from the st short range memory devices that are detected, are written in the input/output frame register. read from the i2c slot marker register is not supported by the crx14. if the i2c host tries to read the slot marker register, the crx14 will return the data valu e ffh in both random address and current address read modes until noack is generated by the i2c host. the result of the detection sequence is stored in the input/output frame register. this register can be read by the host by using i2c random address read. figure 16. host-to-crx14 transfer: i2c write to slot marker register s t a r t 1010xxx n s t o p ack ack answer frame data device select code bus master crx14 write bus slave ai09245 r/w data 1 data 2 answer frame data answer frame data data n answer frame data received frame length ack ack noack ack 03h s t o p ack slot marker register address bus master crx14 write bus slave ai09246 s t a r t 1010xxx device select code r/w ack
crx14 applying the i2c protocol to the crx14 registers doc id 8880 rev 4 25/47 figure 17. crx14-to-host transfer: i2c random address read from slot marker register figure 18. crx14-to-host transfer: i2c current address read from slot marker register 5.5 addresses above location 06h in i2c write mode, when the crx14 receives the 8-bit register address, and the address is above location 06h, the device does not acknowledge (noack) and deselects itself from the bus. the serial data line, sda, stays at logic ?1 ? (pull-up resistor), a nd the i2c host receives a noack during the 9th bit time. the sda line stays high until the stop condition is issued. in the i2c current and random address read modes, when the crx14 receives the 8-bit register address, and the address is above location 06h, the device does not acknowledge the device select code after the start condition, and deselects itself from the bus. s t a r t 1010xxx 00h ffh s t o p ack ack ack slot marker register address device select code bus master crx14 read bus slave ai09247 r e s t a r t 1010xxx r/w device select code r/w noack ffh s t o p ack bus master crx14 read bus slave ai09248 s t a r t 1010xxx device select code r/w noack
crx14 iso14443 type-b radio frequency data transfer crx14 26/47 doc id 8880 rev 4 6 crx14 iso14443 type-b radio frequency data transfer 6.1 output rf data transfer from the crx14 to the picc (request frame) the crx14 output buffer is controlled by the 13.56mhz clock signal generated by the external oscillator and by the request frame generator. the crx14 can be directly connected to an external matching circuit to generate a 13.56mhz sinusoidal carrier frequency on its antenna. the current driven into the antenna coil is directly generated by the crx14 rfout output driver. if the antenna is correctly tuned, it emits an h-field of a large enough magnitude to power a contactless picc from a short distance. the energy received on the picc antenna is converted to a power supply voltage by a regu lator, and turned into data bits by the ask demodulator. the crx14 amplitude modulates the 13.56mhz wave by 10% as represented in figure 19 . the data transfer rate is 106 kbit/s. figure 19. wave transmitted using ask modulation 6.2 transmission format of request frame characters the crx14 transmits characters of 10 bits, with the least significant bit (b 0 ) transmitted first, as shown in figure 20 . several 10-bit characters, preceded by the start of frame (sof) and followed by the end of frame (eof), constitute a request frame, as shown in figure 26 . a request frame includes the sof, instructions, addresses, data, crc and the eof as defined in the iso14443 type-b. each bit duration is called an elementary time unit (etu). one etu is equal to 9.44s (1/106khz). data bit transmitted by the crx14 10% ask modulation of the 13.56mhz wave, generated by the rf out driver transfer time for one data bit is 1/106 khz ai10912 10% ask modulation of the 13.56mhz wave, generated on the crx14 antenna
crx14 crx14 iso14443 type-b radio frequency data transfer doc id 8880 rev 4 27/47 figure 20. crx14 request frame character format 6.3 request start of frame the start of frame (sof) described in figure 21 consists of: a falling edge, followed by ten elementary time units (etu) each containing a logical ?0? followed by a single rising edge followed by two etus, each containing a logical ?1?. figure 21. request start of frame 6.4 request end of frame the end of frame (eof) shown in figure 22 consists of: a falling edge, followed by ten elementary time units (etu) containing each a logical ?0?, followed by a single rising edge. figure 22. request end of frame table 7. crx14 request frame character format bit description value b 0 start bit used to synchronize the transmission b 0 = 0 b 1 to b 8 information byte (instruction, address or data) information byte is sent least significant bit first b 9 stop bit used to indicate the end of the character b 9 = 1 1 etu start '0' lsb msb stop '1' information byte b0 b1 b2 b3 b4 b5 b6 b7 b8 b9 ai09250 b 0 b 1 b 2 b 3 b 4 b 5 b 6 b 7 b 8 b 9 b 10 b 11 etu000000000011 ai09251 b 0 b 1 b 2 b 3 b 4 b 5 b 6 b 7 b 8 b 9 etu0000000000 ai09252
crx14 iso14443 type-b radio frequency data transfer crx14 28/47 doc id 8880 rev 4 6.5 input rf data transfer from the picc to th e crx14 (answer frame) the crx14 uses the iso14443 type-b retro-modulation scheme which is demodulated and decoded by the rf in circuitry. the modulation is obtained by modifying the picc current consumption (load modulation). this load modulation induces an h-field variation, by coupling, that is detected by the crx14 rf in input as a voltage variation on the antenna. the rf in input demodulates this variation and decodes the information received from the picc. data must be transmitted using a 847khz, bpsk modulated sub-carrier frequency, f s , as shown in figure 23 , and as specified in is o14443 type-b. in bpsk, a ll data state transitions (from ?0? to ?1? or from ?1? to ?0?) are encoded by phase shift keying the sub-carrier. figure 23. wave received using bpsk sub-carrier modulation 6.6 transmission format of answer frame characters the picc should use the same character format as that used for output data transfer (see figure 20 ). an answer frame includes the sof, data, crc and th e eof, as illustrated in figure 26 . the data transfer rate is 106 kbit/s. the crx14 will also accept answer frames that do not cont ain the sof and eof delimiters, provided that these frames are correctly set in the parameter register. (see figure 26 ). v dyn v rfin t v offset 1/106khz 1/847khz phase shift v ret load modulation effect on the h-field received on the crx14 rf in input pad picc data bit to be transmitted to the crx14. 847khz bpsk, resulting signal generated by the picc for the load modulation. ai09253
crx14 crx14 iso14443 type-b radio frequency data transfer doc id 8880 rev 4 29/47 6.7 answer start of frame the picc sof must be compliant with the iso14443 type-b, and is shown in figure 24 ten or eleven elementary time units (etu) each containing a logical ?0?, two etus containing a logical ?1?. figure 24. answer start of frame 6.8 answer end of frame the picc eof must be compliant with the iso14443 type-b, and is shown in figure 25 : ten or eleven elementary time units (etu) each containing a logical ?0?, two etus containing a logical ?1? figure 25. answer end of frame 6.9 transmission frame the request frame transmission must be followed by a minimum delay, t 0 (see ta b l e ), in which no ask or bpsk modulation occurs, before the answer frame can be transmitted. t 0 is the minimum time required by the crx14 to switch from transmission mode to reception mode, and should be inserted after each frame. after t 0 , the 13.56mhz carrier frequency is modulated by the picc at 847khz for a minimum time of t 1 (see ta b l e ) to allow the crx14 to synchronize. after t 1 , the first phase transition generated by the picc represents the start bit (?0?) of the answer sof (or the start bit ?0? of the first data character in non sof/eof mode). b 0 b 1 b 2 b 3 b 4 b 5 b 6 b 7 b 8 b 9 b 10 b 11 etu000000000011 ai09254 b 12 1 b 0 b 1 b 2 b 3 b 4 b 5 b 6 b 7 b 8 b 9 b 10 b 11 etu000000000011 ai09254 b 12 1
crx14 iso14443 type-b radio frequency data transfer crx14 30/47 doc id 8880 rev 4 figure 26. example of a complete transmission frame 6.10 crc the 16-bit crc used by the crx14 follows the iso14443 type b recommendation. for further information, please see appendix a on page 44 . the two crc bytes are present in all request and answer frames, just before the eof. the crc is calculated on all the bytes between the sof and the crc bytes. upon transmission of a request from the crx14, the picc verifies that the crc value is valid. if it is invalid, it discards the frame and does not answer the crx14. upon reception of an answer from the picc, the crx14 verifies that the crc value is valid. if it is invalid, it stores the value ffh in the input/output frame register. the crc is transmitted least significant by te first. each byte is transmitted least significant bit first. figure 27. crc tr ansmission rules sof cmd data crc crc eof 12 bits at 106kb/s 10 bits 10 bits 10 bits 10 bits 10 bits sent by the crx14 t 0 64/f s min t 1 80/f s min sync f s = 847.5khz sof data crc crc eof 12 or 13 bits 10 bits 12 or 13 bits 10 bits 10 bits t wdg case of answer frame with sof & eof sent by the picc sync data data crc t wdg case of answer frame without sof & eof data crc t 0 64/f s min t 1 80/f s min 10 bits 10 bits 10 bits 10 bits 10 bits output data transfer using ask modulation input data transfer using 847khz bpsk modulation ai09255 t dr lsbyte msbyte crc 16 (8 bits) crc 16 (8 bits) lsbit msbit lsbit msbit ai09256
crx14 tag access using the crx14 coupler doc id 8880 rev 4 31/47 7 tag access using the crx14 coupler in all the following i2c commands, the last three bits of the device select code can be replaced by any of the three-bit binary values (000, 001, 010, 011, 100, 101, 110, 111). these values are linked to the logic levels applied to the e2, e1 and e0 pads of the crx14. 7.1 standard tag comm and access description standard picc commands, like read and write, are generated by the crx14 using the input/output frame register. when the host needs to send a standard frame command to the picc, it first has to internally generate the complete frame, with the command code followed by the command parameters. only the two crc bytes should not be generated, as the crx14 automatically adds them during the rf transmission. when the frame is ready, the host has to write the request frame into the input/output frame register using the i2c write command specified in figure 13 on page 23 . after the i2c stop condition, the crx14 inserts the i2c bytes in the required iso character format ( figure 20 ) and starts to transmit the request frame to the picc. once the rf transmission is over, the crx14 waits for the picc to send an answer frame. if the picc answers, the characters received ( figure 26 ) are demodulated, decoded and stored into the input/output frame register, as specified in ta b l e 4 . during the entire rf transmission, the crx14 disconnects itself from the i2c bus. on reception of the picc eof, the crx14 checks the crc and reconnects itself to the i2c bus. the host can then get the picc answer frame by issuing an input/output frame register read on the i2c bus, as specified in figures 14 and 15 . if no answer from the picc is detected after a time-out delay, fixed in the parameter register (bits b 5 and b 6 ), the input/output frame register is set as specified in ta b l e 4 . figure 28. standard tag command: request frame transmission s t a r t device select code input/ output register address request frame length tag cmd code param param param s t o p sof eof data 1 data data 2 data n crc crc crx14 sof tag cmd code param param param srx14 eof crc crc i2c rf ai09260 data 1 data data 2 data n 01h n
tag access using the crx14 coupler crx14 32/47 doc id 8880 rev 4 figure 29. standard tag command: answer frame reception figure 30. standard tag command: complete tag access description 7.2 anti-collision tag sequence the crx14 can identify an st short range memory using a propri etary anti-collision system. issuing an i2c write command to the slot marker register ( figure 16 ) causes the crx14 to automatically generate a 16 -slot anti-collision sequence, and to store the identified chip_id in the input/output fram e register, as specified in ta bl e 4 . after receiving the slot marker register i2c write command, the crx14 generates an rf pcall16 command followed by fifteen slot_marker commands, from slot_marker(1) to slot_mar ker(15). after each command, the crx14 waits for a tag answer. if the answer is correctly decoded, the corresponding chip_id is stored in the input/output frame register. if there is no answer, or if the answer is wrong (with a crc error, for example), the crx14 stores an error code in the input/output frame register. at the end of the sequence, the host has to read the input/output frame register to retrieve all the identified chip_ids. s t a r t device select code input/ output register address answer frame length tag data s t o p sof eof data 1 data data 2 data p crc crc tag sof tag data tag data tag data tag data tag eof tag crc tag crc i2c rf ai09261 data 1 data data 2 data p 01h p tag data tag data tag data device select code write i/o register address request frame length request frame bytes i2c start stop crc request frame characters sof eof crc tag answer frame characters sof eof t 0 <--> t 1 <--> device select code read answer frame length request frame bytes start stop rf ai09262
crx14 tag access using the crx14 coupler doc id 8880 rev 4 33/47 figure 31. anti-collision st short range memory sequence (1) 03h i2c s t a r t device select code slot marker register address s t o p sof slot 0 06h 04h crc crc eof sof t 0 <--> t 1 <--> chip_id crc crc eof crx14 sof pcall 16 tag command crc crc crx14 eof tag sof tag chip_id tag crc tag crc tag eof rf i2c sof slot 1 16h crc crc eof sof t 0 <--> t 1 <--> chip_id crc crc eof rf... i2c sof slot 2 26h crc crc eof sof t 0 <--> t 1 <--> chip_id crc crc eof rf... i2c sof slot 3 36h crc crc eof sof t 0 <--> t 1 <--> chip_id crc crc eof rf... i2c sof slot 4 46h crc crc eof sof t 0 <--> t 1 <--> chip_id crc crc eof rf... i2c sof slot 5 56h crc crc eof sof t 0 <--> t 1 <--> chip_id crc crc eof rf... i2c sof slot 6 66h crc crc eof sof t 0 <--> t 1 <--> chip_id crc crc eof rf... i2c sof slot 7 76h crc crc eof sof t 0 <--> t 1 <--> chip_id crc crc eof rf... i2c sof slot 8 86h crc crc eof sof t 0 <--> t 1 <--> chip_id crc crc eof rf... i2c sof slot 9 96h crc crc eof sof t 0 <--> t 1 <--> chip_id crc crc eof rf... crx14 sof slot marker command crc crc crx14 eof tag sof tag chip_id tag crc tag crc tag eof ai09263
tag access using the crx14 coupler crx14 34/47 doc id 8880 rev 4 figure 32. anti-collision st short range memory sequence continued i2c sof slot 10 96h crc crc eof sof t 0 <--> t 1 <--> chip_id crc crc eof rf ... i2c sof slot 11 56h crc crc eof sof t 0 <--> t 1 <--> chip_id crc crc eof rf ... i2c sof slot 12 66h crc crc eof sof t 0 <--> t 1 <--> chip_id crc crc eof rf ... i2c sof slot 13 76h crc crc eof sof t 0 <--> t 1 <--> chip_id crc crc eof rf ... i2c sof slot 14 86h crc crc eof sof t 0 <--> t 1 <--> chip_id crc crc eof rf ... i2c sof slot 15 96h crc crc eof sof t 0 <--> t 1 <--> chip_id crc crc eof rf ... 01h i2c ... s t a r t device select code i/o register address r e s t a r t device select code answer frame length slot 0 chip_id answer status 12h status chip_id chip_id chip_id chip_id chip_id chip_id chip_id chip_id chip_id status slot bits b 0 to b 7 status slot bits b 8 to b 15 slot 1 chip_id answer slot 2 chip_id answer slot 3 chip_id answer slot 4 chip_id answer slot 5 chip_id answer slot 6 chip_id answer slot 7 chip_id answer slot 8 chip_id answer rf i2c ... chip_id chip_id chip_id chip_id chip_id chip_id chip_id rf ai09264 slot 9 chip_id answer slot 10 chip_id answer slot 11 chip_id answer slot 12 chip_id answer slot 13 chip_id answer slot 14 chip_id answer slot 15 chip_id answer s t o p
crx14 maximum rating doc id 8880 rev 4 35/47 8 maximum rating stressing the device above the rating listed in the absolute maximum ratings table may cause permanent damage to the device. exposure to absolute maximum rating conditions for extended periods may affect device relia bility. these are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. refer also to the stmicroelectronics sure program and other relevant quality documents. table 8. absolute maximum ratings symbol parameter value unit t stg storage temperature ?65 to 150 c v io input or output range (sda) ?0.3 to 6.5 v v io input or output range (other pads) ?0.3 to vcc+0.3 v v cc supply voltage ?0.3 to 6.5 v p out output power on antenna output driver (rf out ) 100 mw v esd electrostatic discharge voltage (human body model) (1) 1. mil-std-883c, 3015.7 (100 pf, 1500 ? ). 4000 v electrostatic discharge voltage (machine model) (2) 2. eiaj ic-121 (condition c) (200 pf, 0 ? ) 500 v
dc and ac parameters crx14 36/47 doc id 8880 rev 4 9 dc and ac parameters this section summarizes the operating and measurement conditions, and the dc and ac characteristics of the device. the parameters in the dc and ac characteristic tables that follow are derived from tests performed under the measurement conditions summarized in the relevant tables. designers should check that the operating conditions in their circuit match the measurement conditions when relying on the quoted parameters. figure 33. i2c ac testing i/o waveform 1. sampled only, not 100% tested. 2. t a = 25 c, f = 400khz. table 9. i2c ac measurement conditions parameter min. max. unit v cc supply voltage 4.5 5.5 v ambient operating temperature (t a ) ?20 85 c input rise and fall times 50 ns input pulse voltages 0.2v cc 0.8v cc v input and output timing reference voltages 0.3v cc 0.7v cc v ai09235 0.8v cc 0.2v cc 0.7v cc 0.3v cc table 10. i2c input parameters (1,2) symbol parameter min. max. unit c in input capacitance (sda) 8 pf c in input capacitance (scl, e0, e1, e2)) 6 pf t ns low pass filter input time constant (scl & sda inputs) 100 400 ns table 11. i2c dc characteristics symbol parameter test condition min. max. unit i li input leakage current (scl, sda, e0, e1, e2) 0v ?? v in ? v cc 2 a i lo output leakage current (scl, sda, e0, e1, e2) 0v ? v out ? v cc , sda in hi-z 2 a
crx14 dc and ac parameters doc id 8880 rev 4 37/47 figure 34. i2c ac waveforms i cc supply current v cc = 5 v, f c = 400 khz (rise/fall time < 30ns), rf off 6ma v cc = 5v, f c = 400 khz (rise/fall time < 30ns), rf on 20 ma i cc1 supply current (stand-by) v in = v ss or v cc , v cc = 5 v, rf off 5ma v il input low voltage (scl, sda) ?0.3 0.3v cc v input low voltage (e0, e1, e2) ?0.3 0.3v cc v v ih input high voltage (scl, sda) 0.7v cc v cc + 1 v input high voltage (e0, e1, e2) 0.7v cc v cc + 1 v v ol output low voltage (sda) i ol = 3 ma, v cc = 5 v 0.4 v table 11. i2c dc characteristics (continued) symbol parameter test condition min. max. unit tchcl clch tdlcl tchdx start condition tdxcx tcldx tchdh tdhdl sda input sda change stop & bus free scl sda in scl sda out data valid tclqv tclqx data output scl sda in tchdh trfex tchdx stop condition crx14 command execution start condition ai09236
dc and ac parameters crx14 38/47 doc id 8880 rev 4 table 12. i2c ac characteristics symbol alt. parameter fast i2c 400 khz i2c 100 khz unit minmaxminmax t ch1ch2 (1) 1. sampled only, not 100% tested. t r clock rise time 300 1000 ns t cl1cl2 (1) t f clock fall time 300 300 ns t dh1dh2 (1 ) t r sda rise time 20 300 20 1000 ns t dl1dl2 (1) t f sda fall time 20 300 20 300 ns t chdx (2) 2. for a restart condition, or following a write cycle. t su:sta clock high to input transition 600 4700 ns t chcl t high clock pulse width high 600 4000 ns t dlcl t hd:sta input low to clock low (start) 600 4000 ns t cldx t hd:dat clock low to input transition 0 0 s t clch t low clock pulse width low 1.3 4.7 s t dxcx t su:dat input transition to clock transition 100 250 ns t chdh t su:sto clock high to input high (stop) 600 4000 ns t dhdl t buf input high to input low (bus free) 1.3 4.7 s t clqv t aa clock low to data out valid 1000 3500 ns t clqx t dh data out hold time after clock low 200 200 ns f c f scl clock frequency 400 100 khz
crx14 dc and ac parameters doc id 8880 rev 4 39/47 figure 35. crx14 synchronous timing t rfsbl t rff t rfr b a t por v rfout f cc rf out ask modulated signal 1 0 1 eof data frame transmitted by the crx14 in ask 847khz sof 1 1 0 data 1 0 data 1 0 frame transmitted by the picc in bpsk t dr t dr t 0 t 1 t da t da 0 start t rfsbl t rfsbl t rfsbl t rfsbl t rfsbl t jit t jit t jit t jit t jit data jitter on frame transmitted by the crx14 in ask ai09258 frame transmission between the reader and the contactless device table 13. rf out ac characteristics symbol parameter (1) condition min. max. unit f cc external oscillator frequency v cc = 5 v 13.553 13.567 mhz mi carrier carrier modulation index mi=(a-b)/(a+b) 10 14 % t rfr ,t rff 10% rise and fall time 0.5 1.5 s t rfsbl pulse width on rf out 1 etu = 128/f cc 9.44 s t jit ask modulation bit jitter crx14 to picc -0.5 0.5 s t 0 antenna reversal delay min = 64/f s 75 s t 1 synchronization delay min = 80/f s 94 s
dc and ac parameters crx14 40/47 doc id 8880 rev 4 t wdg answer delay watchdog (b 5 =0, b 6 =0) request eof rising edge to first answer start bit 500 s t wdg answer delay watchdog (b 5 =0, b 6 =1) 5ms t wdg answer delay watchdog (b 5 =1, b 6 =0) 10 ms t wdg answer delay watchdog (b 5 =1, b 6 =1) 309 ms t dr time between request characters crx14 to picc 9.44 s p a rf out output power 90 mw t por crx14 power-on delay 20 ms 1. data specified in the table above are estimated or target values. all values can be updated during product qualification. table 13. rf out ac characteristics (continued) symbol parameter (1) condition min. max. unit table 14. rf in ac characteristics symbol parameter (1) condition min. max. unit t rfsbl picc pulse width 1 etu = 128/f cc 9.44 s f s picc sub-carrier frequency f cc /16 847.5 khz t da time between answer characters picc to crx14 1, 2, 3 etu v dyn rf in dynamic voltage level v dyn max for v offset = v cc /2 0.5 v cc /2 v v offset rf in offset voltage level 23v v ret rf in retro-modulation level 120 mv 1. data specified in the table above are estimated or target values. all values can be updated during product qualification.
crx14 package mechanical doc id 8880 rev 4 41/47 10 package mechanical in order to meet environmental requirements, st offers these devices in different grades of ecopack? packages, depending on their level of environmental compliance. ecopack? specifications, grade definitions and product status are available at: www.st.com. ecopack? is an st trademark
package mechanical crx14 42/47 doc id 8880 rev 4 figure 36. so16 narrow - 16 lead plastic small outline, 150 mils body width, package outline 1. drawing is not to scale. table 15. so16 narrow - 16 lead plastic small outline, 150 mils body width, package mechanical data symbol millimeters inches typ. min. max. typ. min. max. a 1.75 0.0689 a1 0.1 0.25 0.0039 0.0098 a2 1.25 0.0492 b 0.31 0.51 0.0122 0.0201 c 0.17 0.25 0.0067 0.0098 d 9.9 9.8 10 0.3898 0.3858 0.3937 e 6 5.8 6.2 0.2362 0.2283 0.2441 e1 3.9 3.8 4 0.1535 0.1496 0.1575 e 1.27 0.05 h 0.25 0.5 0.0098 0.0197 l 0.4 1.27 0.0157 0.05 k08 08 tolerance millimeters inches ccc 0.1 0.0039 % % ! ! ! c $ b e , k ccc# mm 'ageplane h? 1?-%
crx14 ordering information doc id 8880 rev 4 43/47 11 ordering information for a list of available options (speed, package, etc.) or for further information on any aspect of this device, please contact your nearest st sales office. table 16. ordering information scheme example: crx14 ? mq / xxx device type crx14 package mq = so16 narrow (150 mils width) mqp = so16 narrow (150 mils width) ecopack? customer code xxx = given by the issuer
iso14443 type b crc calculation crx14 44/47 doc id 8880 rev 4 appendix a iso14443 type b crc calculation #include #include #include #include #define byteunsigned char #define ushortunsigned short unsigned short updatecrc(byte ch, ushort *lpwcrc) { ch = (ch^(byte)((*lpwcrc) & 0x00ff)); ch = (ch^(ch<<4)); *lpwcrc = (*lpwcrc >> 8)^((ushort)ch << 8)^((ushort)ch<<3)^((ushort)ch>>4); return(*lpwcrc); } void computecrc(char *data, int length, byte *transmitfirst, byte *transmitsecond) { byte chblock; ushortt wcrc; wcrc = 0xffff; // iso 3309 do { chblock = *data++; updatecrc(chblock, &wcrc); } while (--length); wcrc = ~wcrc; // iso 3309 *transmitfirst = (byte) (wcrc & 0xff); *transmitsecond = (byte) ((wcrc >> 8) & 0xff); return; } int main(void) { byte buffcrc_b[10] = {0x0a, 0x12, 0x34, 0x56}, first, second, i; printf("crc-16 g(x) = x^16 + x^12 + x^5 + 1");
crx14 iso14443 type b crc calculation doc id 8880 rev 4 45/47 printf("crc_b of [ "); for(i=0; i<4; i++) printf("%02x ",buffcrc_b[i]); computecrc(buffcrc_b, 4, &first, &second); printf("] transmitted: %02x then %02x.", first, second); return(0); }
revision history crx14 46/47 doc id 8880 rev 4 revision history table 17. document revision history date revision changes 04-aug-2004 1.0 first issue 23-feb-2005 2.0 document put into new template. 21-jul-2005 3.0 added package information in table 16: ordering information scheme . 01-apr-2010 4 updated table 15: so16 narrow - 16 lead plastic small outline, 150 mils body width, package mechanical data on page 42
crx14 doc id 8880 rev 4 47/47 please read carefully: information in this document is provided solely in connection with st products. stmicroelectronics nv and its subsidiaries (?st ?) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described he rein at any time, without notice. all st products are sold pursuant to st?s terms and conditions of sale. purchasers are solely responsible for the choice, selection and use of the st products and services described herein, and st as sumes no liability whatsoever relating to the choice, selection or use of the st products and services described herein. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. i f any part of this document refers to any third party products or services it shall not be deemed a license grant by st for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoev er of such third party products or services or any intellectual property contained therein. unless otherwise set forth in st?s terms and conditions of sale st disclaims any express or implied warranty with respect to the use and/or sale of st products including without limitation implied warranties of merchantability, fitness for a parti cular purpose (and their equivalents under the laws of any jurisdiction), or infringement of any patent, copyright or other intellectual property right. unless expressly approved in writing by an authorized st representative, st products are not recommended, authorized or warranted for use in milita ry, air craft, space, life saving, or life sustaining applications, nor in products or systems where failure or malfunction may result in personal injury, death, or severe property or environmental damage. st products which are not specified as "automotive grade" may only be used in automotive applications at user?s own risk. resale of st products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by st for the st product or service described herein and shall not create or extend in any manner whatsoev er, any liability of st. st and the st logo are trademarks or registered trademarks of st in various countries. information in this document supersedes and replaces all information previously supplied. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners. ? 2010 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - philippines - singapore - spain - sweden - switzerland - united kingdom - united states of america www.st.com

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